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1990, 1993, 1995 data sheet description the m pd431000a is a high speed, low power, and 1,048,576 bits (131,072 words 8 bits) cmos static ram. the m pd431000a has two chip enable pins (ce1, ce2) to extend the capacity. and battery backup is available. in addition to this, a and b versions are wide voltage versions. the m pd431000a is packed in 32-pin plastic dip, 32-pin plastic sop, and 32-pin plastic tsop(i). features ? 131,072 words by 8 bits organization ? fast access time: 70, 85, 100, 120, 150, 250 ns (max.) ? wide voltage range (a version: v cc = 3.0 v to 5.5 v, b version: v cc = 2.7 v to 5.5 v) ? 2 v (min.) data retention ? output enable input for easy application ? two chip enable inputs: ce1, ce2 access time operating operating standby data retention part number ns (max.) supply voltage temperature supply current supply current note 1 v c m a (max.) m a (max.) m pd431000a-l 70, 85 4.5 to 5.5 0 to 70 100 15 m pd431000a-ll 20 3 m pd431000a-a 70 note 2 , 100, 120 3.0 to 5.5 13 note 3 m pd431000a-b 70 note 2 , 100, 120, 150 2.7 to 5.5 11 note 4 notes 1. t a 40 c 2. v cc = 4.5 to 5.5 v 3. 20 m a (v cc > 3.6 v) 4. 20 m a (v cc > 3.3 v) m pd431000a mos integrated circuit the information in this document is subject to change without notice. 1m-bit cmos static ram 128k-word by 8-bit the mark shows major revised points. document no. m11657ej6v0ds00 (6th edition) date published december 1997 n cp(k) printed in japan
2 m pd431000a 32-pin plastic dip (600 mil) ordering information access time operating operating part number package ns (max.) supply voltage temperature remark v c m pd431000acz-70l 70 4.5 to 5.5 0 to 70 l version m pd431000acz-85l 85 m pd431000acz-70ll 70 ll version m pd431000acz-85ll 85 m pd431000agw-70l 70 l version m pd431000agw-85l 85 m pd431000agw-70ll 70 ll version m pd431000agw-85ll 85 m pd431000agw-a10 100 3.0 to 5.5 a version m pd431000agw-a12 120 m pd431000agw-b10 100 2.7 to 5.5 b version m pd431000agw-b12 120 m pd431000agw-b15 150 m pd431000agz-70ll-kjh 70 4.5 to 5.5 ll version m pd431000agz-a10-kjh 100 3.0 to 5.5 a version m pd431000agz-a12-kjh 120 m pd431000agz-b10-kjh 100 2.7 to 5.5 b version m pd431000agz-b12-kjh 120 m pd431000agz-b15-kjh 150 m pd431000agz-70ll-kkh 70 4.5 to 5.5 ll version m pd431000agz-a10-kkh 100 3.0 to 5.5 a version m pd431000agz-a12-kkh 120 m pd431000agz-b10-kkh 100 2.7 to 5.5 b version m pd431000agz-b12-kkh 120 m pd431000agz-b15-kkh 150 m pd431000agu-70ll-9jh 70 4.5 to 5.5 ll version m pd431000agu-a10-9jh 100 3.0 to 5.5 a version m pd431000agu-a12-9jh 120 m pd431000agu-b10-9jh 100 2.7 to 5.5 b version m pd431000agu-b12-9jh 120 m pd431000agu-b15-9jh 150 m pd431000agu-70ll-9kh 70 4.5 to 5.5 ll version m pd431000agu-a10-9kh 100 3.0 to 5.5 a version m pd431000agu-a12-9kh 120 m pd431000agu-b10-9kh 100 2.7 to 5.5 b version m pd431000agu-b12-9kh 120 m pd431000agu-b15-9kh 150 32-pin plastic sop (525 mil) 32-pin plastic tsop (i) (8 20 mm) (normal bent) 32-pin plastic tsop (i) (8 20 mm) (reverse bent) 32-pin plastic tsop (i) (8 13.4 mm) (normal bent) 32-pin plastic tsop (i) (8 13.4 mm) (reverse bent)
3 m pd431000a pin configuration (marking side) nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc a15 ce2 we a13 a8 a9 a11 oe a10 ce1 i/o8 i/o7 i/o6 i/o5 i/o4 m a11 a9 a8 a13 we ce2 a15 v cc nc a16 a14 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 oe a10 ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 m 32-pin plastic tsop (i) (8 20mm) (normal bent) [ pd431000agz-kjh] 32-pin plastic dip (600 mil) [ pd431000acz] 32-pin plastic sop (525 mil) [ pd431000agw] oe a10 ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a11 a9 a8 a13 we ce2 a15 v cc nc a16 a14 a12 a7 a6 a5 a4 32-pin plastic tsop (i) (8 20mm) (reverse bent) [ pd431000agz-kkh] a0 to a16 i/o1 to i/o8 ce1, ce2 we oe v cc gnd nc : address inputs : data inputs/outputs : chip enable 1, 2 : write enable : output enable : power supply : ground : no connection m m
4 m pd431000a a11 a9 a8 a13 we ce2 a15 v cc nc a16 a14 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 oe a10 ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 m 32-pin plastic tsop (i) (8 13.4mm) (normal bent) [ pd431000agu-9jh] oe a10 ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a11 a9 a8 a13 we ce2 a15 v cc nc a16 a14 a12 a7 a6 a5 a4 32-pin plastic tsop (i) (8 13.4mm) (reverse bent) [ pd431000agu-9kh] m a0 to a16 i/o1 to i/o8 ce1, ce2 we oe v cc gnd nc : address inputs : data inputs/outputs : chip enable 1, 2 : write enable : output enable : power supply : ground : no connection
5 m pd431000a block diagram truth table ce1 ce2 oe we mode i/o supply current h i sb l l h h h output disable l h l h read d out lh l write d in remark : don't care not selected high impedance address buffer row decoder memory cell array 1,048,576 bits input data controller a0 a16 i/o1 i/o8 sense/switch column decoder output data controller address buffer ce1 ce2 oe we v cc gnd i cca
6 m pd431000a electrical specifications absolute maximum ratings supply voltage v cc C0.5 note to +7.0 v input/output voltage v t C0.5 note to v cc + 0.5 v operating ambient temperature t a 0 to 70 c storage temperature t stg C55 to +125 c note C3.0 v (min.) (pulse width 30 ns) caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational sections of this characteristics. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions (1/2) m pd431000a-l m pd431000a-ll min. max. min. max supply voltage v cc 4.5 5.5 3.0 5.5 v high level input voltage v ih 2.2 v cc + 0.5 2.2 v cc + 0.5 v low level input voltage v il C0.3 note +0.8 C0.3 note +0.5 v operating ambient temperature t a 070070 c note C3.0 v (min.) (pulse width 30 ns) recommended operating conditions (2/2) m pd431000a-b parameter symbol min. max. unit supply voltage v cc 2.7 5.5 v high level input voltage v ih 2.2 v cc + 0.5 v low level input voltage v il C0.3 note +0.5 v operating ambient temperature t a 070 c note C3.0 v (min.) (pulse width 30 ns) parameter symbol rating unit m pd431000a-a parameter symbol unit
7 m pd431000a standby supply current high level output voltage low level output voltage min. typ. max. min. typ. max. min. typ. max. dc characteristics (recommended operating conditions unless otherwise noted) (1/2) m pd431000a-l m pd431000a-ll m pd431000a-a parameter symbol test conditions unit input leakage i li v in = 0 v to v cc C1.0 +1.0 C1.0 +1.0 C1.0 +1.0 m a current i/o leakage i lo v i/o = 0 v to v cc , C1.0 +1.0 C1.0 +1.0 C1.0 +1.0 m a current ce1 = v ih or ce2 = v il or we = v il or oe = v ih operating supply i cca1 ce1 = v il , ce2 = v ih 40 70 40 70 40 70 ma current minimum cycle time i i/o = 0 ma v cc 3.6 v 35 i cca2 ce1 = v il , ce2 = v ih ,151515 i i/o = 0 ma v cc 3.6 v 8 i cca3 ce1 0.2 v, ce2 3 v cc C 0.2 v, 10 10 10 cycle = 1 mhz, i i/o = 0 ma, v il 0.2 v, v ih 3 v cc C 0.2 v v cc 3.6 v 8 i sb ce1 = v ih or ce2 = v il 333ma v cc 3.6 v 2 i sb1 ce1 3 v cc C 0.2 v, 2 100 1 20 1 20 m a ce2 3 v cc C 0.2 v v cc 3.6 v 0.5 13 i sb2 ce2 0.2 v 2 100 1 20 1 20 v cc 3.6 v 0.5 13 v oh1 i oh = C1.0 ma, v cc 3 4.5 v 2.4 2.4 2.4 v i oh = C0.5 ma 2.4 v oh2 i oh = C0.02 ma v ol1 i ol = 2.1 ma, v cc 3 4.5 v 0.4 0.4 0.4 v i ol = 1.0 ma 0.4 v ol2 i ol = 0.02 ma 0.1 remark these dc characteristics are in common regardless of package types and access time. v cc C0.1
8 m pd431000a dc characteristics (recommended operating conditions unless otherwise noted) (2/2) m pd431000a-b parameter symbol test conditions unit input leakage i li v in = 0 v to v cc C1.0 +1.0 m a current i/o leakage i lo v i/o = 0 v to v cc , C1.0 +1.0 m a current ce1 = v ih or ce2 = v il or we = v il or oe = v ih operating supply i cca1 ce1 = v il , ce2 = v ih 40 70 ma current minimum cycle time i i/o = 0 ma v cc 3.3 v 30 i cca2 ce1 = v il , ce2 = v ih ,15 i i/o = 0 ma v cc 3.3 v 7 i cca3 ce1 0.2 v, ce2 3 v cc C 0.2 v, 10 cycle = 1 mhz, i i/o = 0 ma, v il 0.2 v, v ih 3 v cc C 0.2 v v cc 3.3 v 7 i sb ce1 = v ih or ce2 = v il 3ma v cc 3.3 v 2 i sb1 ce1 3 v cc C 0.2 v, 1 20 m a ce2 3 v cc C 0.2 v v cc 3.3 v 0.5 11 i sb2 ce2 0.2 v 1 20 v cc 3.3 v 0.5 11 v oh1 i oh = C1.0 ma, v cc 3 4.5 v 2.4 v i oh = C0.5 ma 2.4 v oh2 i oh = C0.02 ma v cc C 0.1 v ol1 i ol = 2.1 ma, v cc 3 4.5 v 0.4 v i ol = 1.0 ma 0.4 v ol2 i ol = 0.02 ma 0.1 remark these dc characteristics are in common regardless of package types and access time. capacitance (t a = 25 c, f = 1 mhz) parameter symbol test conditions min. typ. max. unit input capacitance c in v in = 0 v 6 pf input/output capacitance c i/o v i/o = 0 v 10 pf remarks 1. v in : input voltage 2. these parameters are periodically sampled and not 100 % tested. low level output voltage high level output voltage standby supply current min. typ. max.
9 m pd431000a ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions input waveform (rise/fall time 5 ns) input pulse levels 0.8 v to 2.2 v : m pd431000a-l, 431000a-ll 0.5 v to 2.2 v : m pd431000a-a, 431000a-b output waveform output load ac characteristics should be measured with the following output load conditions. part number output load conditions t aa , t co1 , t co2 , t oe , t oh t lz1 , t lz2 , t olz , t hz1 , t hz2 , t ohz , t whz , t ow m pd431000a-a10, 431000a-a12 1ttl + 50 pf 1ttl + 5 pf m pd431000a-b10, 431000a-b12 m pd431000a-b15 1ttl + 100 pf 1ttl + 5 pf m pd431000a-l, 431000a-ll see figure 1 see figure 2 figure 1 figure 2 remark c l includes capacitances of the probe and jig, and stray capacitances. 1.5 v 1.5 v test points 1.5 v 1.5 v test points +5 v i/o (output) 1.8 k w 100 pf c l 990 w +5 v i/o (output) 1.8 k w 5 pf c l 990 w
10 m pd431000a read cycle (1/2) v cc 3 4.5 v v cc 3 3.0 v m pd431000a-70 parameter symbol m pd431000a-a m pd431000a-85 m pd431000a-a10 m pd431000a-a12 unit condition m pd431000a-b min. max. min. max. min. max. min. max. read cycle time t rc 70 85 100 120 ns address access time t aa 70 85 100 120 ns note ce1 access time t co1 70 85 100 120 ns ce2 access time t co2 70 85 100 120 ns oe to output valid t oe 35 45 50 60 ns output hold from address change t oh 10 10 10 10 ns ce1 to output in low impedance t lz1 10 10 10 10 ns ce2 to output in low impedance t lz2 10 10 10 10 ns oe to output in low impedance t olz 5555ns ce1 to output in high impedance t hz1 25 30 35 40 ns ce2 to output in high impedance t hz2 25 30 35 40 ns oe to output in high impedance t ohz 25 30 35 40 ns note see the output load . remark these ac characteristics are in common regardless of package types and l, ll versions. read cycle (2/2) v cc 3 2.7 v parameter symbol m pd431000a-b10 m pd431000a-b12 m pd431000a-b15 unit condition min. max. min. max. min. max. read cycle time t rc 100 120 150 ns address access time t aa 100 120 150 ns note ce1 access time t co1 100 120 150 ns ce2 access time t co2 100 120 150 ns oe to output valid t oe 50 60 70 ns output hold from address change t oh 10 10 10 ns ce1 to output in low impedance t lz1 10 10 10 ns ce2 to output in low impedance t lz2 10 10 10 ns oe to output in low impedance t olz 555ns ce1 to output in high impedance t hz1 35 40 50 ns ce2 to output in high impedance t hz2 35 40 50 ns oe to output in high impedance t ohz 35 40 50 ns note see the output load . remark these ac characteristics are in common regardless of package types and l, ll versions.
11 m pd431000a read cycle timing chart remark in read cycle, we should be fixed to high level. t hz2 t rc t oh t hz1 t olz t oe t lz2 t co2 t lz1 t co1 t ohz t aa hi-z data out oe (input) ce2 (input) ce1 (input) address (input) i/o (output)
12 m pd431000a write cycle (1/2) v cc 3 4.5 v v cc 3 3.0 v m pd431000a-70 parameter symbol m pd431000a-a m pd431000a-85 m pd431000a-a10 m pd431000a-a12 unit condition m pd431000a-b min. max. min. max. min. max. min. max. write cycle time t wc 70 85 100 120 ns ce1 to end of write t cw1 55 70 80 100 ns ce2 to end of write t cw2 55 70 80 100 ns address valid to end of write t aw 55 70 80 100 ns address setup time t as 0000ns write pulse width t wp 50 60 60 85 ns write recovery time t wr 5500ns data valid to end of write t dw 35 35 60 60 ns data hold time t dh 0000ns we to output in high impedance t whz 25 30 35 40 ns note output active from end of write t ow 5555ns note see the output load . remark these ac characteristics are in common regardless of package types and l, ll versions. write cycle (2/2) v cc 3 2.7 v parameter symbol m pd431000a-b10 m pd431000a-b12 m pd431000a-b15 unit condition min. max. min. max. min. max. write cycle time t wc 100 120 150 ns ce1 to end of write t cw1 80 100 120 ns ce2 to end of write t cw2 80 100 120 ns address valid to end of write t aw 80 100 120 ns address setup time t as 000ns write pulse width t wp 60 85 100 ns write recovery time t wr 000ns data valid to end of write t dw 60 60 80 ns data hold time t dh 000ns we to output in high impedance t whz 35 40 50 ns note output active from end of write t ow 555ns note see the output load . remark these ac characteristics are in common regardless of package types and l, ll versions.
13 m pd431000a write cycle timing chart 1 (we controlled) cautions 1. during address transition, at least one of pins ce1, ce2, we should be inactivated. 2. when i/o pins are in the output state, do not apply to the i/o pins signals that are opposite in phase with output signals. remarks 1. write operation is done during the overlap time of a low level ce1, we, and a high level ce2. 2. if ce1 changes to low level at the same time or after the change of we to low level, or if ce2 changes to high level at the same time or after the change of we to low level, the i/o pins will remain high impedance state. 3. when we is at low level, the i/o pins are always high impedance. when we is at high level, read operation is executed. therefore oe should be at high level to make the i/o pins high impedance. t wc t cw1 t aw t wp t as t wr t whz t dw t dh t ow indefinite data out high impe- dance high impe- dance data in indefinite data out address(input) ce1 (input) we (input) i/o (input/output) ce2 (input) t cw2
14 m pd431000a cautions 1. during address transition, at least one of pins ce1, ce2, we should be inactivated. 2. when i/o pins are in the output state, do not apply to the i/o pins signals that are opposite in phase with output signals. remark write operation is done during the overlap time of a low level ce1, we, and a high level ce2. write cycle timing chart 2 (ce1 controlled) t wc t as t cw1 t aw t wp t wr t dw t dh data in high impedance address (input) ce1 (input) we (input) i/o (input) high impedance ce2 (input) t cw2
15 m pd431000a write cycle timing chart 3 (ce2 controlled) t wc t as t cw2 t aw t wp t wr t dw t dh data in high impedance address (input) ce2 (input) we (input) i/o (input) high impedance ce1 (input) t cw1 cautions 1. during address transition, at least one of pins ce1, ce2, we should be inactivated. 2. when i/o pins are in the output state, do not apply to the i/o pins signals that are opposite in phase with output signals. remark write operation is done during the overlap time of a low level ce1, we, and a high level ce2.
16 m pd431000a low v cc data retention characteristics l version ( m pd431000a-l: t a = 0 to 70 c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v ccdr1 ce1 3 v cc C 0.2 v, ce2 3 v cc C 0.2 v 2.0 5.5 v v ccdr2 ce2 0.2 v 2.0 5.5 data retention supply current i ccdr1 v cc = 3.0 v, ce1 3 v cc C 0.2 v, 1 50 note m a ce2 3 v cc C 0.2 v or ce2 0.2 v i ccdr2 v cc = 3.0 v, ce2 0.2 v 1 50 note chip deselection to data t cdr 0ns retention mode operation recovery time t r 5ms note 15 m a (t a 40 c) ll version, a version, and b version ( m pd431000a-ll, 431000a-a, 431000a-b: t a = 0 to 70 c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v ccdr1 ce1 3 v cc C 0.2 v, ce2 3 v cc C 0.2 v 2.0 5.5 v v ccdr2 ce2 0.2 v 2.0 5.5 data retention supply current i ccdr1 v cc = 3.0 v, ce1 3 v cc C 0.2 v, 0.5 10 note m a ce2 3 v cc C 0.2 v or ce2 0.2 v i ccdr2 v cc = 3.0 v, ce2 0.2 v 0.5 10 note chip deselection to data t cdr 0ns retention mode operation recovery time t r 5ms note 3 m a (t a 40 c)
17 m pd431000a data retention timing chart (1) ce1 controlled note a version: 3.0 v, b version: 2.7 v remark on the data retention mode by controlling ce1, the input level of ce2 must be ce2 3 v cc C 0.2 v or ce2 0.2 v. the other pins (address, i/o, we, oe) can be in high impedance state. (2) ce2 controlled note a version: 3.0 v, b version: 2.7 v remark the other pins (ce1, address, i/o, we, oe) can be in high impedance state. t cdr data retention mode 5.0 v v ih (min. ) v ccdr (min. ) v il (max. ) t r v cc ce1 ce1 3 v cc ?0.2 v gnd 4.5 v note t cdr data retention mode 5.0 v v ih (min. ) v ccdr (min. ) v il (max. ) t r v cc ce2 ce2 0.2 v gnd 4.5 v note
18 m pd431000a package drawings 32pin plastic dip (600 mil) notes 1) each lead centerline is located within 0.25 mm (0.01 inch) of its true position (t.p.) at maximum material condition. item millimeters inches a 40.64 max. 1.600 max. b 1.27 max. 0.050 max. c 2.54 (t.p.) 0.100 (t.p.) d 0.50?.10 0.020 +0.004 ?.005 f 1.1 min. 0.043 min. g 3.2?.3 0.126?.012 j 5.08 max. 0.200 max. k 15.24 (t.p.) 0.600 (t.p.) m 0.25 0.010 +0.004 ?.003 n 0.25 0.01 h 0.51 min. 0.020 min. i 4.31 max. 0.170 max. l 13.2 0.520 +0.10 ?.05 2) item "k" to center of leads when formed parallel. p32c-100-600a-1 r 0~15 0~15 p 0.9 min. 0.035 min. 32 17 116 n b i m r m c d f h g a j k l p
19 m pd431000a 32 pin plastic sop (525 mil) a 32 17 detail of lead end 116 3 +7 ? p32gw-50-525a item millimeters inches a b c d e f g h i j k 20.61 max. 1.27 (t.p.) 2.95 max. 2.7 14.1 0.3 0.78 max. 0.812 max. 0.006 0.117 max. 0.555 0.012 0.445 0.031 max. note l m 0.12 0.8 0.2 1.4 0.2 11.3 0.005 0.031 +0.009 ?.008 each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 0.055 0.008 0.106 0.050 (t.p.) 0.20 0.008 n 0.10 0.004 0.016 0.40 0.15 0.05 +0.004 ?.002 +0.10 ?.05 +0.004 ?.003 +0.10 ?.05 f d m c m b n g e h k l j i
20 m pd431000a notice of change in 32-pin plastic tsop (i) (8 20 mm) standoff height we are changing the 32-pin plastic tsop (i) (8 20 mm) standoff height 0.05 0.05 mm (low standoff height) to 0.1 0.05 mm (high standoff height). each lot version is identified by the fifth character of the lot number. difference between high standoff height and low standoff height detail of lead end normal bent reverse bent q high standoff height: q = 0.1 ?.05 mm low standoff height: q = 0.05 ?.05 mm q identification of each lot version each lot version is identified by the fifth character of the lot number. fifth character of the lot number lot version standoff height r r version 0.1 0.05 mm (high standoff height) h h version 0.05 0.05 mm (low standoff height) marking example japan lot number d431000a xxxx xxxx
21 m pd431000a high standoff height notes 32 pin plastic tsop ( i ) (8 20) item millimeters inches a b c e i 8.0?.1 0.5 (t.p.) 0.1?.05 0.45 max. k 1.2 max. 18.4?.1 0.145?.05 f 0.10 m 0.315?.004 0.018 max. 0.004?.002 0.724 0.006 0.048 max. 0.004 0.020 (t.p.) d 0.22?.05 0.009 2. each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 3. "a" excludes mold flash. (includes mold flash : 8.3 mm max. <0.327 inch max.>) c r d m m l +0.002 ?.003 0.97?.08 g 0.038 +0.004 ?.003 +0.005 ?.004 l 0.5 0.020 0.10 n 0.004 p 20.0?.2 0.787 +0.009 ?.008 q3 3 +5 ? +5 ? 0.25 r 0.010 s32gz-50-kjh1 s 0.60?.15 0.024 +0.006 ?.007 +0.002 ?.003 j 0.8?.2 0.031 +0.009 ?.008 1 16 32 17 s p g f e s q n k i b detail of lead end j a s 1. controlling dimension millimeter.
22 m pd431000a high standoff height notes 32 pin plastic tsop ( i ) (8 20) item millimeters inches a b c e i 8.0?.1 0.5 (t.p.) 0.1?.05 0.45 max. k 1.2 max. 18.4?.1 0.145?.05 f 0.10 m 0.315?.004 0.018 max. 0.004?.002 0.724 0.006 0.048 max. 0.004 0.020 (t.p.) d 0.22?.05 0.009 2. each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 3. "a" excludes mold flash. (includes mold flash : 8.3 mm max. <0.327 inch max.>). c r d m m g +0.002 ?.003 0.97?.08 g 0.038 +0.004 ?.003 +0.005 ?.004 l 0.5 0.020 0.10 n 0.004 p 20.0?.2 0.787 +0.009 ?.008 q3 3 +5 ? +5 ? 0.25 r 0.010 s32gz-50-kkh1 s 0.60?.15 0.024 +0.006 ?.007 +0.002 ?.003 j 0.8?.2 0.031 +0.009 ?.008 1 16 32 17 s n b a f e q s l k i p j detail of lead end s 1. controlling dimension millimeter.
23 m pd431000a 32 pin plastic tsop ( i ) (8 20) s32gz-50-kjh-3 item millimeters inches notes (1) each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. d n i 18.4?.2 0.724 +0.009 ?.008 k 0.125 0.005 l 0.5?.1 0.020 +0.004 ?.005 detail of lead end r c b b c 0.5 (t.p.) 0.45 max. 0.018 max. 0.020 (t.p.) d g 1.02 max. 0.20?.10 0.008?.004 0.041 max. j 0.8?.2 0.031 +0.009 ?.008 q 0.05?.05 0.002?.002 r s 1.1 max. 5 ? 5 ? 0.044 max. +0.10 ?.05 +0.004 ?.002 (2) "a" exciudes mold flash. (includes mold flash : 8.3 mm max. < 0.327 inch max. > ) m m q g l k 1 16 32 17 s p i j h a a 8.0?.1 0.315?.004 h 19.0?.2 0.748?.008 m n 0.10 0.08 0.003 0.004 p 20.0?.2 0.787 +0.009 ?.008 low standoff height
24 m pd431000a 32 pin plastic tsop ( i ) (8 20) s32gz-50-kkh-3 item millimeters inches notes (1) each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. d n i 18.4?.2 0.724 +0.009 ?.008 k 0.125 0.005 l 0.5?.1 0.020 +0.004 ?.005 detail of lead end r c b b c 0.5 (t.p.) 0.45 max. 0.018 max. 0.020 (t.p.) d g 1.02 max. 0.20?.10 0.008?.004 0.041 max. j 0.8?.2 0.031 +0.009 ?.008 q 0.05?.05 0.002?.002 r s 1.1 max. 5 ? 5 ? 0.044 max. +0.10 ?.05 +0.004 ?.002 (2) "a" exciudes mold flash. (includes mold flash : 8.3 mm max. < 0.327 inch max. > ) m m q g l k j a 8.0?.1 0.315?.004 h 19.0?.2 0.748?.008 m n 0.10 0.08 0.003 0.004 p 20.0?.2 0.787 +0.009 ?.008 1 16 32 17 s p i h a low standoff height
25 m pd431000a 32pin plastic tsop ( i ) (8x13.4) note (1) each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. item millimeters inches p32gu-50-9jh b 0.45 max. 0.018 max. c 0.5 (t.p.) 0.02 (t.p.) detail of lead end a 8.0?.1 0.315?.004 h 12.4?.2 0.488?.008 b t n d 0.22?.05 0.009 +0.002 ?.003 g 1.0?.05 0.039 +0.003 ?.009 i 11.8?.1 0.465 +0.004 ?.005 j 0.8?.2 0.031 +0.009 ?.008 k l 0.5 0.020 m 0.08 0.003 n 0.08 0.003 q 0.1?.05 0.004?.002 p 13.4?.2 0.528 +0.008 ?.009 s 1.2 max. 0.048 max. r3 3 t 0.25 0.01 u 0.16?.15 0.006 +0.007 ?.006 +5 ? +5 ? (2) "a" excludes mold flash. (includes mold flash : 8.3 mm max. <0.331 inch max.>) m u l r q s d m c g k j 1 16 32 17 a 0.145 +0.025 ?.015 0.006?.001 h p i
26 m pd431000a 32pin plastic tsop ( i ) (8x13.4) note (1) each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. item millimeters inches p32gu-50-9kh b 0.45 max. 0.018 max. c 0.5 (t.p.) 0.02 (t.p.) detail of lead end a 8.0?.1 0.315?.004 h 12.4?.2 0.488?.008 b t n d 0.22?.05 0.009 +0.002 ?.003 g 1.0?.05 0.039 +0.003 ?.009 i 11.8?.1 0.465 +0.004 ?.005 j 0.8?.2 0.031 +0.009 ?.008 k l 0.5 0.020 m 0.08 0.003 n 0.08 0.003 q 0.1?.05 0.004?.002 p 13.4?.2 0.528 +0.008 ?.009 s 1.2 max. 0.048 max. r3 3 t 0.25 0.01 u 0.16?.15 0.006 +0.007 ?.006 +5 ? +5 ? (2) "a" excludes mold flash. (includes mold flash : 8.3 mm max. <0.331 inch max.>) 1 16 32 17 m u l r q s d m c g a k j h p i 0.145 +0.025 ?.015 0.006?.001
27 m pd431000a recommended soldering conditions the following conditions must be met when soldering conditions of the m pd431000a. for more details, refer to our document semiconductor device mounting technology manual (c10535e) . please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. types of surface mount device m pd431000agw : 32-pin plastic sop (525 mil) m pd431000agz-kjh : 32-pin plastic tsop(i) (8 20 mm) (normal bent) m pd431000agz-kkh : 32-pin plastic tsop(i) (8 20 mm) (reverse bent) m pd431000agu-9jh : 32-pin plastic tsop(i) (8 13.4 mm) (normal bent) m pd431000agu-9kh : 32-pin plastic tsop(i) (8 13.4 mm) (reverse bent) please consult with our sales offices type of through hole mount device m pd431000acz: 32-pin plastic dip (600 mil) soldering process soldering conditions wave soldering solder temperature: 260 c or below, (only to leads) flow time: 10 seconds or below partial heating method pin temperature: 300 c or below, time: 3 seconds or below (per one lead) caution do not jet molten solder on the surface of package.
28 m pd431000a [memo]
29 m pd431000a [memo]
30 m pd431000a [memo]
31 m pd431000a notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
2 m pd431000a [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

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